New HBF spec outlines tech that can give GPUs terabytes of extra memory — Sandisk and SK hynix unveil spec with up to 16-Hi NAND stacks, 3 TB/s bandwidth, UCIe
SanDisk and SK hynix introduced the High Bandwidth Flash (HBF) specification, developed jointly and released via the Open Compute Project as an open standard. Initial HBF packages target up to 512GB using 8-Hi or 16-Hi NAND stacks, with bandwidth grades around 0.4 to 3.0 TB/s, and integration via UCIe or an xPU-HBF interface. The spec is not yet officially published by OCP.
How this was made
The 30-second read
Why it matters
The spec targets up to 512GB packages using 8-Hi or 16-Hi NAND stacks and bandwidth grades up to about 3 TB/s, with integration claims around UCIe (SK hynix) or an xPU-HBF interface (Sandisk). The key trading question is customer adoption, since many major players are reported as not interested so far.
Market read
This is a technology standard release with quantified performance targets, but no immediate customer commitments or financial implications are disclosed.
What to watch
The article does not specify latency, cost per GB, power, or qualification timelines; those factors may determine whether HBF meaningfully competes with HBM4 or existing SSD/DRAM tiers.
Background
Sandisk and SK hynix jointly introduced the High Bandwidth Flash (HBF) specification through the Open Compute Project (OCP) as an open standard combining 3D NAND non-volatility with high-bandwidth interfaces inspired by HBM.
Ticker impact
Sandisk (SNDK) and SK hynix introduced the HBF spec via OCP, targeting up to 512GB packages and up to 3 TB/s bandwidth for AI inference memory tiers.
Near-term impact likely limited until customers commit; medium-term optionality for NAND/stacked storage demand tied to AI inference.
The article is a technology/spec release with no named customer adoption, no financial guidance, and no immediate production ramp details.
The article notes Micron (MU) has so far expressed no interest in HBF, implying competitive positioning versus this proposed NAND-HBM memory tier.
No direct trading catalyst for MU; any impact would be indirect and contingent on future consortium participation or alternative roadmaps.
The text provides only a stated lack of interest, with no quantified market share, product timeline, or customer commitments.
Sandisk claims HBF may adopt an xPU-HBF interface aligned with UCIe implementations by companies like Broadcom (AVGO), linking HBF integration to broader chiplet interconnect ecosystems.
Likely negligible for AVGO absent a direct deal, product, or customer design win.
AVGO is mentioned only as an example of UCIe implementers, not as a named participant or beneficiary.
Market effects
Could pressure the AI memory hierarchy narrative by offering NAND-based, near-memory bandwidth tiers that may complement or partially substitute for HBM economics in inference.
No clear regional demand signal; likely global supply-chain implications for NAND and advanced packaging.
Standardization via OCP could accelerate cross-vendor interoperability, influencing global AI server memory architecture roadmaps.
Counterpoint
HBF may remain a niche standard if major AI platform buyers do not adopt it, limiting any real revenue impact for NAND suppliers.
Key entities
- companySandisk
Co-developer of the HBF specification, positioning it as a new memory tier for AI inference workloads.
- companySK hynix
Co-developer of HBF, claiming use of UCIe to simplify integration with heterogeneous computing platforms.
- organizationOpen Compute Project (OCP)
Forum through which the HBF specification was released as an open standard.
- technology_standardUCIe
Chiplet interconnect standard referenced as a basis for HBF integration.
