PCIe Prepares for the 3D Era
Synopsys has developed a 3D PCIe Gen 6 test chip, addressing challenges in high-speed data transfer for AI workloads. The chip uses face-to-face stacking and through-silicon vias to maintain signal integrity, aiming to support advanced 3D chip designs in data centers. Synopsys highlights the need for collaboration with customers to optimize the technology for commercial use.
How this was made

The 30-second read
Why it matters
Synopsys' 3D test chip validates its IP for next‑generation AI data‑center products, but no commercial deals are disclosed.
Market read
Technical progress may benefit Synopsys and its customers in AI and data‑center markets, but immediate trading impact is minimal.
What to watch
Potential design‑win risks, cost of 3D packaging, and competition from other IP vendors.
Background
The article discusses the technical challenges and solutions for implementing PCIe Gen6 in 3D‑stacked packages, featuring quotes from Synopsys executives.
Ticker impact
Synopsys announced a 3D PCIe Gen6 test chip demonstrating 64 GT/s per lane and 128 GB/s over an eight‑lane link.
Limited short‑term price effect; long‑term upside if customers adopt the technology.
While technically significant, the announcement lacks immediate commercial contracts or revenue guidance.
Market effects
May accelerate adoption of 3D‑stacked chiplet designs across AI accelerators and data‑center silicon.
Primarily U.S. semiconductor IP market; limited immediate regional effect.
Relevant to global data‑center and AI hardware supply chains.
Counterpoint
Without announced customer wins, the demo may not translate into near‑term revenue for Synopsys.
Key entities
- CompanySynopsys
Leading supplier of semiconductor IP, developer of the 3D PCIe Gen6 test chip.
- ExecutiveManmeet Walia
Executive Director of Product Management at Synopsys, quoted on PCIe challenges.
- ExecutiveMadhumita Sanyal
Senior Director of Technical Product Management at Synopsys, discussed the 3D test chip.

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