Synopsys validates a PCIe 6.0 PHY inside a face-to-face 3D stack at 64 GT/s — says it got there by pulling apart an existing 2D test chip
Synopsys announced a 3D PCIe 6.0 test chip with 64 GT/s per lane and 128 GB/s bandwidth, using PAM4 signaling. The company adapted an existing 2D chip, adding through-silicon vias and redesigning circuits for 3D stacking. Challenges include routing signals and managing errors, with future shifts to 3.5D packaging and UCIe expected.






